1. Field of the Invention
This invention relates to a buffer circuit, and more particularly, to a buffer circuit that may be used in digital devices or systems.
2. Background of the Invention
Buffers are commonly used in data transmission systems. For example, a signal buffer circuit may be used at an input interface to receive or amplify signals, enhance signal driving capability, and/or reduce signal transition time.
Buffer circuits are usually designed using analog circuits. An example of an analog buffer circuit may include a differential pair with various passive elements, including inductors, capacitors and resistors. FIG. 1A shows an analog buffer circuit 100A for Pseudo Emitter Coupled Logic (PECL). The PECL buffer 100A of FIG. 1A has input terminals 102 and 112, which receive separate PECL signals that are complementary to each other. The input terminal 102 is connected to the gate of an NMOS transistor 106, which is coupled to a PMOS transistor 104 having its gate coupled to ground. The input terminal 112 is connected to the gate of an NMOS transistor 116, which is coupled to a PMOS transistor 114 having its gate coupled to ground. The PMOS transistors 104 and 114 have their sources connected to a power supply Vdd (e.g., +4 volts). The drain of the PMOS transistor 104 is connected to the drain of the NMOS 106, and the drain of the PMOS transistor 114 is connected to the drain of the NMOS transistor 116. The sources of the NMOS transistors 106 and 116 are connected to the NMOS transistor 130 which may provide a constant current. The drain of the PMOS transistor 104 is connected to an output terminal 140 via an NMOS transistor 108 which serves as a level shifter. The drain of the PMOS transistor 114 is connected to an output terminal 150 via an NMOS transistor 118 which serves as a level shifter. Similar to the NMOS transistor 130, the NMOS transistors 132 and 134 serve as a current source to provide constant current sources. The PECL buffer 100A constitutes a current switching differential buffer circuit. Such a circuit may also be designed to reduce signal swing and optimize signal differential, thus improving the operating bandwidth and noise tolerance. A feedback circuit to compensate certain parameters, such as bias, bandwidth and gain, may be employed to prevent process drift from affecting product yield.
Although an analog buffer circuit may provide high efficiency in certain applications, such circuit has complicated designs, consumes more power, and requires large circuit areas. Thus, some systems use digital circuits instead to reduce power consumption and circuit area. However, digital circuits may suffer from poor noise tolerance. In addition, when digital circuits operate in high frequency, the resulting switching noise may decrease the system efficiency.
FIG. 1B shows a digital buffer disclosed in U.S. Pat. No. 6,483,347. The buffer circuit 100B of FIG. 1B may include eight inverters arranged as illustrated. The inverters 12 and 22 form a differential inverter pair. The inverters 40 and 50 constitute self bias circuit. The inverters 60 and 70 form a common mode noise-rejection circuit.